1. Field of the Invention
The present invention relates to output buffers and, more particularly, to CMOS output buffers which are tolerant to voltage variation.
2. Description of Related Art
The trend in modern CMOS transistor circuit design is toward lower operating voltages to achieve reduced power consumption. For several years, 5 volt CMOS transistors were very common and circuits were designed to operate at this voltage level. More recently, 3 volt CMOS transistors have become more common. However, since 5 volt circuitry is still very commonplace, it is desirable that a CMOS component such as an output buffer be able to operate at 3 volts and yet tolerate a 5 volt operating voltage without damage or significant performance degradation. In other words, a voltage range tolerant output buffer is needed for applications where 3 volt devices may be used in a 5 volt environment.
One type of conventional tri-state CMOS output buffer is depicted in FIG. 1A as buffer 10. Depending on the state of the input signals provided to buffer 10, the output of buffer can exhibit a 0, a 1, or a high impedance (HI Z) State. When a tri-state output buffer such as buffer 10 exhibits a high impedance state, it is said to be exhibiting the "tri-state condition". Buffer 10 includes CMOS transistors M1, M2, M3 and M4, the interconnection of which is later described in more detail. Buffer 10 includes two inputs, designated PUP and PD, to which quasi-complementary data signals having the same names as the respective inputs are provided. PUP refers to a pull-up signal and PD refers to a pull-down signal. Except for those times when the PUP signal and the PD signal are both low, the PUP signal is high when the PD signal is lowland vice versa. Unlike true complementary input signals, it is possible for both the PUP and PD signals to be low at the same time which causes the output of the buffer to exhibit the high impedance (HI Z) state. FIG. 1B is a truth table illustrating the above described combinations of states for output buffer 10.
Buffer 10 includes an output pad 15 as shown. In an ideal output buffer, when PUP is high, output pad 15 is pulled up completely to the rail voltage, V.sub.CC.
Conversely, when PD is high, output pad 15 would ideally be completely pulled down to the V.sub.SS or ground voltage. Also, in the ideal case, if both PUP and PD are low, buffer 10 is tri-stated such that output pad 15 is permitted to float in a high impedance or "hi-Z" state. It is very desirable that the output buffer exhibit a low input capacitance to permit the buffer to operate at high speed. Unfortunately, the conventional output buffer 10 depicted in FIG. 1A exhibits a relatively high input capacitance and thus low speed performance.
In buffer 10 transistor M1 is a PMOS enhancement mode device and transistor M2 is an NMOS depletion mode device. Transistor M3 is a NMOS enhancement mode device and transistor M4 is an NMOS enhancement mode device. Transistor M4 acts as a pull-down device for buffer 10. In other words, when a high PD signal is supplied to buffer 10, transistor M4 pulls down the source of M2 which pulls down output pad 15 to ground. Transistor M3 is configured as a source follower, the gate of which is coupled to the PUP input and the source of which is coupled to output pad 15. The threshold voltage of source follower M3 is defined to be VT. A characteristic of a source follower such as transistor M3 is that the voltage on the source follows the voltage on the gate minus a differential of approximately VT. In other words, when you pull up on the gate of the source follower, the source voltage follows the gate voltage up. However, once the source voltage is high, the assistance of another active device (here, pull-down transistor M4) is typically required to pull the source low again as described above.
In buffer 10, source follower M3 and pull-down transistor M4 act together to attempt to cause the output pad 15 voltage (the source of transistor M3) to follow the PUP input signal which is presented to the gate of source follower M3. In actual practice, the source of N channel source follower M3 is pulled down to ground by transistor M4 when PD is high better than it is pulled up to V.sub.CC when PD is low and PUP is high. In other words if the PUP signal goes low and the PD signal goes high to turn pull-down transistor M4 on, then the source of source follower M3 also goes low or nearly to ground voltage. Unfortunately, however, when the PUP signal goes high to V.sub.CC, the source of source follower M3 does not pull up completely to V.sub.CC, but rather only pulls up to approximately V.sub.CC minus VT.
Series coupled transistors M1 and M2 are employed in buffer 10 to provide additional current paths to permit the buffer output voltage at output pad 15 to be pulled up nearly all the way to V.sub.CC when the PUP input goes high to V.sub.CC. More particularly, transistor M1 provides the extra pull-up capability while transistor M2 provides a high voltage (5 volt) tolerance capability. To illustrate this point, consider FIG. 2 which shows an output buffer 20. Output buffer 20 of FIG. 2 is similar to output buffer 10 of FIG. 1A, except that transistor M2 is not present in output buffer 20. An inverter 25 is coupled between the PUP input and the gate of transistor M1 in both buffers 10 and 20.
Without transistor M2 present, output buffer 20 becomes a "not 5 volt tolerant" output buffer. In output buffer 20, transistor M1 provides additional current to pull output pad 15 to nearly V.sub.CC when PUP goes high. In this manner, transistor M1 assists source follower M3 in pulling pull output pad 15 up. However, while output buffer 20 is capable of having its output pad 15 being pulled all the way up to V.sub.CC, output buffer 20 is not 5 volt tolerant due to the lack of transistor M2. More particularly, buffer 20 of FIG. 2 is not 5 volt tolerant because a parasitic diode 30 is effectively formed between the drain of transistor M1 and the n well in which the drain of transistor Mi is formed. For convenience in illustration a box with a dashed line is drawn around diode 30 to indicate that, while drawn separately from transistor M1, diode 30 is actually a part of transistor M1.
FIG. 3 is a physical representation of pull-up transistor M1 which shows parasitic diode 30 with more clarity. Pull-up transistor M1 includes a substrate 35 in which an n-well 40 is situated. A p+ source 45 (designated S) and a p+ drain 50 (designated D) are situated in spaced-apart relationship at the upper surface of n well 40. A gate region 55 is situated between p+ source 45 and p+ drain 50 as shown in FIG. 3. The p+ junction between p+ drain 50 and n well 40 effectively forms a parasitic diode which is represented schematically as diode 30. If a user applies 5 volts to output pad 15 of transistor M1 in output buffer 20, parasitic diode 30 will be turned on and conduct current. If the buffer is only a 3.3 volt component and 5 volts is applied to output pad 15, this causes a drop 1.7 volts across the diode. A large amount of current would thus be conducted by the diode in buffer 20 if the output pad is subjected to 5 volts instead of 3 volts, Thus, the presence of parasitic diode 30 connected to output pad 15 in buffer 20 causes buffer 20 to be "not 5 volt tolerant".
To make the output buffer "5 volt tolerant", a depletion mode NMOS transistor M2 is coupled in series with transistor M1 as in output buffer 10 of FIG. 1A. In this manner, transistor M2 acts as an isolation transistor which effectively decouples parasitic diode 30 from output pad 15 such that should the user or circuit designer apply 5 volts to output pad 15, diode 30 is not turned on. If an enhancement mode NMOS transistor were used for isolation transistor M2, such a transistor would hinder the ability of transistor M1 to pull output pad 15 all the way up to V.sub.CC. For this reason, a depletion mode NMOS transistor is used as transistor M2. Unfortunately, another problem is created by placing a depletion mode NMOS transistor M2 in series with transistor M1. Depletion mode NMOS transistors exhibit very poor sub-threshold current characteristics and, in fact, have a negative threshold voltage. In other words, depletion mode NMOS transistors do not turn off very well and are said to exhibit current leakage. The leakage path through transistor M2 and parasitic diode 30 typically only occurs if the voltage applied to pad 15 goes above V.sub.CC. However, depletion mode NMOS transistor M2 will not turn off unless a sufficiently negative voltage is applied between the gate and source of transistor M2. Thus, the gate of such a transistor must generally be pulled all the way to ground to assure that the transistor is completely off and does not leak.
FIG. 1C depicts the driven state output level at pad 15 and corresponding states of isolation transistor M2. Isolation transistor M2 is off when the driven output level at pad 15 is a 0 or low. Isolation transistor M2 is also off when the driven output level at pad 15 is in the "HI Z" state. However, isolation transistor M2 is on when the driven output level at pad 15 is 1 or high state. It is thus seen that isolation transistor M2 switches state with each transition of the PUP input signal.
Depletion mode NMOS transistor M2 is typically a rather wide device. For example, the channel width of transistor M2 is approximately 320 microns wide in one version. When the gate of such a wide device as NMOS transistor M2 is coupled to the PUP input, a significant amount of capacitance is provided to the PUP input. Unfortunately, this capacitive loading of the PUP input significantly loads down the PUP signal which is a data signal provided to the buffer. The capacitive effects of transistor M2 on this PUP input data signal are felt as the PUP signal supplied to transistor M2 is gated on and off to turn transistor M2 on and off. In other words, the capacitance exhibited by transistor M2 on the PUP input signal is encountered each time transistor M2 changes state in step with the transitions of the PUP input signal. This capacitive loading of the PUP input causes the propagation delay of data through output buffer 10 to be undesirably increased. For example, the propagation delay of a conventional output buffer such as shown in FIG. 1A is approximately 1.7 nsec. An output buffer which would provide 5 volt tolerance and yet exhibit minimal capacitive loading of the input signal would be very desirable.